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MIL-STD-1553 RT Front End FPGA Core

MIL-STD-1553B Notice 2 Remote Terminal front end Core for FPGA Devices

Feature Summary:

• MIL-STD-1553B Notice 2 Remote Terminal (RT).
• Suitable for any MIL-STD-1553 Remote Terminal implementation.
• CPU host interface not needed.
• Best gate count in the industry.
• Supports any whole number clock frequency.
• Connects to any transceiver-transformer pair.
• Full MIL-STD-1553 Validation test passed in 3rd party tester.
• Unique licensing method with no initial payment. Very cost effective for small amounts.
• Vendor and technology independent IEEE-1076 VHDL design and coding.

RT Block Diagram:

Back End Interface

The 1553 RT front-end core interfaces the backend with a simple address-data read and write “bus cycles”. For each word requested by a transmit command, the core introduces a read cycle very much like a CPU.

For a receive command, the core produces a write cycle. The user can build a FIFO mechanism or simple registers in his FPGA to interface this simplified backend interface.
This core is best used where CPU is not required.

Gate Count

Vendor	Family	Used logic
Altera	Cyclone	823 LEs
Altera	Stratix	820 LEs
Xilinx	Spartan2E	490 Slices
Xilinx	Virtex II	487 Slices

Manchester Decoder

The unique Manchester decoder can work with any whole number clock frequency from 12Mhz and up. (For example it could work with a PCI interface's 66 Mhz clock)

Transceivers

Sital Technology's 1553 RT core connects to any standard transceiver-transformer pair. The core was fully validated with a 3rd party dual transceiver.

RT Validation

Sital Technology's 1553 RT core has been successfully implemented in a 3rd party FPGA, and has passed the full MIL-STD-1553B Notice 2 RT Validation test plan in an independent laboratory.

*	DDC® and MINI-ACE® are registered trademarks of Data Device Corporation, Bihemia, NY, USA. There is not any affiliation between Data Device Corporation and Sital technology, Ltd.