MIL-STD-1553B Notice 2 Remote Terminal (RT).
	Compatible with Industry standard Enhanced DDC Mini-ACE host interface mapping and functionality.
	Best gate count in the industry.
	Supports any whole number clock frequency.
	Connects to any transceiver-transformer pair.
	Full MIL-STD-1553 Validation test passed in 3rd party tester.
	Unique licensing method with no initial payment. Very cost effective for small amounts.
	Vendor and technology independent IEEE-1076 VHDL design and coding.

RT Block Diagram

Host Interface
The remote terminal host interface memory and register map is compatible with DDC's enhanced mini ACE* Remote Terminal mapping. For reasons of FPGA space optimization, not all of DDC's features were implemented. The 4 communication modes of operation, single buffer, dual buffer, circular buffer and global circular buffer modes are controllable on a sub-address by sub-address manner compatible with DDC's memory mapping. FPGAs, being a flexible technology allows Sital to add additional compatibility features if such are required.

Gate Count

Manchester Decoder
The unique Manchester decoder can work with any whole number clock frequency from 12Mhz and up. (For example it could work with a PCI interface's 66 Mhz clock)

Transceivers
Sital Technology's 1553 RT core connects to any standard transceiver-transformer pair. The core was fully validated with a 3rd party dual transceiver.

RT Validation
Sital Technology's 1553 RT core has been successfully implemented in a 3rd party FPGA, and has passed the full MIL-STD-1553B Notice 2 RT Validation test plan in an independent laboratory.

	Download product brochure
	Download validation test results