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FPGA Verification |
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Active-HDL™ is a Windows® based integrated FPGA Design and Simulation solution. Active-HDL includes a full HDL graphical design tool suite and RTL/gate-level mixed-language Simulator. |
ASIC/FPGA Verification |
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ALINT™ is an RTL design analysis tool that identifies design issues early in the development cycle. VHDL, Verilog® or mixed-language designs are checked for coding inconsistencies, design structure issues, synthesis, simulation, clock and reset issues prior to simulation and synthesis. |
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Riviera-PRO is a multi-platform, high-performance, mixed-language RTL and gate-level simulator for ASIC and FPGA designs. Riviera-PRO includes advanced debugging tools and support of advanced verification methodologies with SystemC and SystemVerilog, Assertions Based Verification (ABV), Transaction Level Modeling (TLM) and VHDL/Verilog Design Rule Checking. |
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ALDEC HDL
