SOC-VSP by Carbon Design Systems
Carbon design systems delivers software that enable RTL to be used as an integral part of a system validation strategy. Carbon turns RTL into a virtual system prototype that enables engineers to easily validate their design architecture, software, and hardware months before their physical prototypes and ICs can be fabricated.
With Carbon's compiler and wizard technology, RTL (Verilog/VHDL) can be automatically imported as a high performance compiled object into any C/SystemC compliant simulator and debug environment.
For the first time there is a flow that provides accurate HW profiling, integrated SW debug, and execution of SW on HW before silicon exists. Now you can maximize the value of your diverse RTL assets:.
Using Carbon's breakthrough RTL (Verilog® and VHDL) compilation technology, simulation speeds can be achieved that were not thought possible.
Software Developers can get an early jump on debugging and validating their embedded software executing on a Carbon hardware-accurate model. Linking in your favorite software debugger is easy through Carbon's C API.
Validating firmware, software drivers, and diagnostics can be completed before tapeout, rather than waiting months for silicon or an idealized behavioral model to be developed.
Carbon's SOC-VSP with ARM's RealView® is the first all-software environment that integrates simultaneous software and hardware debugging-the first complete ESL solution.
Inspect any hardware register or memory, while stepping through software code running on one or more processors.
Fully debug complex interactions between the hardware and the software. Does a strange value appear in a peripheral's register? Set a breakpoint on the hardware register and see what code was executing on the processor at that breakpoint.
If you find a bug in the hardware, waveforms can be displayed in RealView® or easily dumped in VCD or FSDB formats for later inspection.
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ALDEC HDL