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MIL-STD-1553 BC, RT, MT

DDC^® Enhanced MINI-ACE^® compatible core for FPGA and ASIC Devices

The BRM1553D IP Core is suitable for any Mil-Std-1553 implementation. The core incorporates a backend logic that arranges the messages in a predefined memory structure, which simplifies the interface between the 1553 bus and the local CPU. The BRM1553D core can act as a replacement (2nd source) for DDC® Enhanced MINI-ACE® devices as the data is arranged in the same way.

Feature Summary:

• MIL-STD-1553B Notice 2 Bus Controller (BC), Remote Terminal (RT) and Monitor (MT).
• Compatible with Industry standard Enhanced DDC^® MINI-ACE^® host interface mapping and functionality.
• Best gate count in the industry.
• Supports any whole number clock frequency.
• Connects to any transceiver-transformer pair.
• Full MIL-STD-1553 Validation test passed in 3rd party tester.
• Unique licensing method with no initial payment. Very cost effective for small amounts.
• Vendor and technology independent IEEE-1076 VHDL design and coding.

RT Block Diagram:

Host Interface

The remote terminal host interface memory and register map is compatible with DDC's^® enhanced MINI-ACE^® Remote Terminal mapping. For reasons of FPGA space optimization, not all of DDC's^® features were implemented. The 4 communication modes of operation, single buffer, dual buffer, circular buffer and global circular buffer modes are controllable on a sub-address by sub-address manner compatible with DDC's^® memory mapping. FPGAs, being a flexible technology allows Sital to add additional compatibility features if such are required.

Gate Count

Vendor	Family	Used logic
Altera	Cyclone	1,510 LEs
Altera	Stratix	1,506 LEs
Xilinx	Spartan2E	893 Slices
Xilinx	Virtex II	890 Slices

Manchester Decoder

The unique Manchester decoder can work with any whole number clock frequency from 12Mhz and up. (For example it could work with a PCI interface's 66 Mhz clock)

Transceivers

Sital Technology's 1553 RT core connects to any standard transceiver-transformer pair. The core was fully validated with a 3rd party dual transceiver.

RT Validation

Sital Technology's 1553 RT core has been successfully implemented in a 3rd party FPGA, and has passed the full MIL-STD-1553B Notice 2 RT Validation test plan in an independent laboratory.

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*	DDC® and MINI-ACE® are registered trademarks of Data Device Corporation, Bohemia, NY, USA. There is not any affiliation between Data Device Corporation and Sital technology, Ltd.