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Seminars Form

Sital is interested in improving services to its customers.
Throughout 2008 we intend to provide technical and informational seminars on subjects that will be interesting for our customers. You can help us improve by selecting the topics that may be of interest to you.

Good Practice in HW Design:      Analyzing design complexity for Reducing development time Power optimization of RTL Design using simulation VHDL/Verilog Board Level Simulation (VBOLS) Clock-Domain-Crossing Design and Verification Basic rules for designing an IP core and design reuse
HDL Designer:      HDL Designer - general Project management with HDL Designer System Verilog in HDL Designer DesignChecker - static checking and analysis tool DO 254 and requirements traceability
ModelSim / Questa:      Modelsim - general Advanced simulation and debugging using ModelSim x5 to x10 RTL Simulation acceleration using high-level libraries Questa and SystemVerilog - general Assertion Based Verification Verification Management, Test Ranking & Analysis Advanced Verification Methodology (AVM & OVM) Questa Verification Library (QVL) PowerAware simulation CodeLink HW/SW simulation and debug of ARM Design
Precision:      Precision - general Incremental Synthesis & P&R flow Physical Aware Synthesis Synthesis and Design using Vendor independent code On-Chip Debug and Verification through JTAG
PCB Tools:      PADS - general PADS Layout PCB Routing Strategies PCB Rules, Advanced Rules PCB RF Design Why choose PADS
Signal Integrity:      HyperLynx - general Fundamentals of High-Speed Design SerDES and DDR / DDR2 Design Controlling Crasstalk in High-Speed PCB design Power Integrity with HyperLynx
Intellectual Property:      IPextreme – CPU, Controllers & Peripheral IP cores Mil-Std-1553 IP cores & Products
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