Please don't hesitate to contact us for any technical question, or design need. 09-7633300 / 04-6442071 You can also take a look at the following technical notes. For licensing and installation support, contact: Duli Yariv duli@sital.co.il / tel. 052-2482332. Hila Gabay hila@sital.co.il / tel. 052-3437142 For technical and design support, contact: Ofer Hofman ofer.h@sital.co.il / tel. 052-2614373. Nir Hamzani nir@sital.co.il / tel. 052-2851104. Ofer Shragay ofer.s@sital.co.il / tel. 052-3734248. Yoav Cohen yoav@sital.co.il / tel. 052-8201757. Technical Notes Important Note: In order to download a document, please click your mouse right button on the required doc and select 'Save Target As...'. Please Avoid opening these PDF in your Internet browser. VHDL Gate_level Simulation: . For HDL Designer users: o Altera VHDL Gate level Simulation o Xilinx VHDL Gate level Simulation . For ModelSim stand alone users: o Altera Max-Plus2 VHDL Gate level Simulation o Altera Quartus VHDL Gate level Simulation o Xilinx VHDL Gate level Simulation Verilog Gate_level Simulation: . For HDL Designer users: o Altera Verilog Gate level Simulation o Xilinx Verilog Gate level Simulation . For ModelSim stand alone users: o Altera Verilog Gate level Simulation o Xilinx Verilog Gate level Simulation Implementing Altera & Xilinx Cores in HDL Designer . VHDL: o Using Xilinx VHDL Cores in HDL Designer o Using Altera VHDL Cores in HDL Designer . Verilog: o Using Xilinx Verilog Cores in HDL Designer o Using Altera Verilog Cores in HDL Designer Leonardo: o Setting Internal Clocks and Buffers o Setting pin_numbers for ports o Adding Xilinx chip scope to your design ModelSim: o How to perform Verilog Gate-Level simulation with Zero Delay? o SignalSpy- Monitoring Internal Signals in a VHDL/Verilog Testbench ... Download Signal Spy VHDL Example ... Download Signal Spy Verilog Example o How to use the "when" command to stop simulation run. VHDL: o Package for Random numbers generation   Technical Notes from Sital More Technical Notes for Modelsim.