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Basic VHDL course

Highly Successful VHDL course intended for companies or individuals who want to evolve into VHDL development. The 4 day practical course presents the latest methods available for successful design of ASIC and FPGA using VHDL. Each training day is compromised of theoretical lectures and practical hands-on exercises. The course is aimed at learning the VHDL language and is independent of any particular simulation tool. The graduates will be able to use any simulation or synthesis tools that have VHDL capabilities.

The course deals with the following VHDL subjects:
Language basics, RTL and top-down design, Synthesis topics, Simulation & Verification issues.

More than 60 courses (1000 students) have already been given in the last 5 years.

Students will receive the course slides book.

The 4 day course is instructed at SELA School (Near Ramat-Gan mall) by SITAL Technology.

For confirmation and registration, please call Merav at SELA:
03-6176133.

The Course contents:

• Introduction to VHDL: Review of design methods, Top down design methodology, Definition of Simulation and Synthesis, Hierarchic designing.
• VHDL top level forms: Entity, Package, Architecture, Library, Configuration, Component Instantiation, Test Bench.
• Behavioral designing: Process, Variables Vs Signals, VHDL Commands, VHDL Syntax, VHDL Operators.
• State machine in VHDL: Mealy machine, Moore & Full moore machine, One hot machine.
• The art of synthesis: Legal forms for synthesis, Resources utilization.
• Advanced topics: Back annotation, Gate level simulation, VITAL and SDF Format, VHDL 93, FATE - Fully Automatic Test Environment.

For Detailed Learning Program, please call Merav at SELA:
03-6176133.