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Advanced Verilog course

Advanced Verilog Design Seminar intended for Verilog designers who wish to acquire comprehensive skills both in hardware design using Verilog for synthesis, and in Test Bench development using advanced simulation constructs for better verification.
Part of the seminar deals with the newly revision of the Verilog language (IEEE 1364-2001) commonly called "Verilog-2001". This new revision adds significant new enhancements for both Verilog Verification-Simulation and Synthesis needs. Topics like enhance I/O file mechanism, new compiler directives, advanced synthesis coding, multi dimensional arrays, signed variables and more will help you to write more efficient Verilog in a shorter time.
SystemVerilog, which enables the modeling and verification of systems at a high level of abstraction, will be overviewed as well.

Participants must have background in Verilog coding for simulation & synthesis.

This 1 day seminar is instructed at SELA School (Near Ramat-Gan mall) by SITAL Technology.

For confirmation and registration, please call Merav at SELA:
03-6176133.

The Course contents:

• Advanced Verilog Topics: Overview, The Verilog evolution, Verilog 2001 major changes, System Verilog overview.
• Verilog 2001: Module declaration, Parameters & Parameters override, Localparam, Signed variable, Arrays, Always block, New operators, Numbers representation, Generate statement, Compiled libraries management.
• New System Tasks and Compiler Directives: Compiler directives, System tasks (Signed, Unsigned, Random, File IO operations, Strings, Simulation controls, VCD).
• New Functions and Tasks: Tasks format, Automatic tasks, Functions format, Automatic Functions, Constant Functions.
• Synthesis Simulation Mismatches: Simulation cycle, Delay assignments, Synthesis mismatch (Sensitivity list, Races, Pragmas (Translate, Full case, Parallel case), X Value).
• Gate-Level Timing Simulation Issues: Specify Block (Path delay, Error and Reject, Timing checks, Timing checks - stability, Timing checks - control), SDF (IO path delay, Parameters override, Overcoming gate-level false warnings), Advanced Simulation Control.
• Advanced Verilog Simulation Environment: · FATE - Fully Automated Test Environment, Simulating BFM – Bus Functional Model ,Monitoring results (Built-in checker, Logging outputs), Speed up Simulation (Compilation/Simulation switches, Performance Analysis).

For Detailed Learning Program, please call Merav at SELA:
03-6176133.