Advanced VHDL & Hardware Design course intended for VHDL designers who would like to acquire comprehensive skills both in digital hardware design using VHDL for synthesis and in test bench development using advanced simulation constructs for better verification.
The objective is to increase engineers productivity by enhancing their VHDL coding and development skills.
Participants must have background in VHDL design including practical experience in designing at least 1 complete device, with testing, simulation & synthesis.
The 2 day course is instructed at SELA School (Near Ramat-Gan mall) by SITAL Technology.
For confirmation and registration, please call Merav at SELA:
03-6176133.
The Course contents:
- Advanced VHDL Language Topics: Overview, Packages & Casting, File I/O mechanism, Advanced Statements, VHDL 93, Functions & Procedures, Attributes, Configurations.
- Advanced Simulation Techniques: Stimulus from vectors file, Monitoring internal signals, Generating random numbers, Simulating BFM – Bus Functional Model, Speed up Simulation.
- VHDL Board Level Simulation (VBoLS): Advantages of doing VBoLS, VBoLS design flow, Model types for board components, VHDL language challenges in VBoLS.
- Advanced Consideration in Digital Design: Digital Design Complexity, Multiple clock domains designs, Handling asynchronous or unpredictable inputs, Synchronizers & FIFOs.
- Advanced topics in VHDL for Synthesis: Common RTL coding errors, Black boxes & cores usage, procedures & Function in Synthesis, Using hierarchy to control synthesis, team work, Incremental/Partial synthesis and P&R Constraints, false paths, optimization options, State machine encoding optimization Retiming / Pipelining / Behavioral synthesis.
- Gate Level Simulation issues: VITAL, SDF, FF example, Simulation challenges.
For Detailed Learning Program, please call Merav at SELA:
03-6176133.
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