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Basic Verilog course

Highly Successful Verilog course intended for companies or individuals who want to evolve into Verilog development. The 3 day practical course presents the latest methods available for successful design of ASIC and FPGA using Verilog.
Each training day is compromised of theoretical lectures and practical hands-on exercises. The course is aimed at learning the Verilog language and is independent of any particular simulation tool. The graduates will be able to use any simulation or synthesis tools that have Verilog capabilities.

The course deals with the following Verilog subjects: Language basics, RTL and top-down design, Synthesis topics, Simulation & Verification issues.

Students will receive:

• The course slides book

The 3 day course is instructed at SELA School (Near Ramat-Gan mall) by SITAL Technology.

For confirmation and registration, please call Merav at SELA:
03-6176133.

The Course contents:

• Introduction to Verilog: Course objectives, Hierarchic design, Simulation, Compilation, and Synthesis terms.
• Module: Structure of Basic Verilog Program, Defining Module: Port list, Port modes, Parameters, Instance Types: order, name.
• Data Types: Value Set, Types of NET, Strength, Types of REG: integer, real, time, Parameters and Parameters Overriding, Number Representation.
• Data Flow: Continuos Assignments, Implicit Continuos Assignment.
• Procedural Blocks: always - Synthesis Writing: Blocking assignment, Non-blocking assignment. always- Simulation Writing: Delay control @,#,->,wait, Initial- Structure and Example, Nested blocks, Block naming & disabling, Intra Assignments.
• Language Statements: if else, case casex casez, Loop(while, repeat, forever, for), assign deassign, force, release.
• Lexical Conventions: Language Operators, Concatenation and Replication, Case Sensitivity, Identifiers & Escape Identifiers, Strings & Comments.
• Compiler directives & system tasks: display control, simulation control, File managing.
• State Machines: Meally, Moore, One Hot.
• Gate Level: Primitives in Verilog, Vendor Libraries, UDP.

For Detailed Learning Program, please call Merav at SELA:
03-6176133.