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Verilog Introduction Seminar for VHDL Designers

The Verilog introduction seminar is intended for VHDL designers who would like to have basic knowledge of the Verilog language. The course is mostly relevant for companies who are using the VHDL language as their main development language but still have the need to include some Verilog components in their project. (As a result of purchased cores, test environement, co-simulation need, etc..). The 1-day seminar covers the fundamental principles of the Verilog language and the constructs most commonly used in a Verilog design.

The course deals with the following Verilog subjects: The Verilog environment, Language concept, basic structure & statements, PLI simulation.

This seminar is not intended for VHDL designers who would like to develop in Verilog!! No practical exercises are included in this seminar. People who would like to design in Verilog should participate in the 3 days Basic Verilog course.

Students will receive photocopies of the transparencies shown in the course.

The seminar (1 day long) is held at the customer site for a group of maximum 20 people.

The seminar engages theoretical lectures in the following subjects:

• Introduction to Verilog.
• Design objects and main language concepts.
• Data Types.
• Continuous Assignment.
• Procedural Blocks.
• Basic Statements.
• Language Operators.
• System Tasks.
• Introduction to PLI.