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VHDL Introduction Seminar for Verilog Designers

The VHDL introduction seminar is intended for Verilog designers who would like to have basic knowledge of the VHDL language. The course is mostly relevant for companies who are using the Verilog language as their main development language but still have the need to include some VHDL components in their project. (As a result of purchased cores, test environement, co-simulation need, etc..). The 1-day seminar covers the fundamental principles of the VHDL language and the constructs most commonly used in a VHDL design.

The course deals with the following VHDL subjects: The VHDL environment, Language concept, basic structure & statements, gate-level simulation.

This seminar is not intended for Verilog designers who would like to develop in VHDL!! No practical exercises are included in this seminar. People who would like to design in VHDL should participate in the 4 days Basic VHDL course.

Students will receive photocopies of the transparencies shown in the course.

The seminar (1 day long) is held at the customer site for a group of maximum 20 people.

The seminar engages theoretical lectures in the following subjects:

• Introduction to VHDL.
• Design objects and main language concepts.
• The VHDL environment.
• The architecture structure.
• Basic statements.
• Gate-Level simulation.
• VHDL design examples.